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Computer Organization
OVERVIEW
CEA CAPA Partner Institution: Universidad Carlos III de Madrid
Location: Madrid, Spain
Primary Subject Area: Computer Engineering
Instruction in: English
Course Code: 13885
Transcript Source: Partner Institution
Course Details: Level 300
Recommended Semester Credits: 3
Contact Hours: 42
DESCRIPTION
The program is composed by the following items:
1. Introduction to computation in parallel. Concept of parallelism and historic evolution.
2. General organization of a computer.
3. Conditions for the parallelism and analysis of the abilities. Analysis of dependencies. Levels of parallelism process and size of the grain. Characteristics of the performance. Theory performance models.
4. Segmentation fundaments. Basic concepts about segmentation.
Structures for controlling functional segmented units.
5. Segmented processors. Basic stages of a segmented processor with a static instructions planning. Types of risks and their possible solutions. Multicicle performance. Dynamic instructions planning. Dynamic jumps prediction.
6. Superscalar structures, supersegmented and VLIW. Superscalar and supersegmented processor concept. Uses of a superscalar processor and of supersegmented ones. VLIW processors.
1. Introduction to computation in parallel. Concept of parallelism and historic evolution.
2. General organization of a computer.
3. Conditions for the parallelism and analysis of the abilities. Analysis of dependencies. Levels of parallelism process and size of the grain. Characteristics of the performance. Theory performance models.
4. Segmentation fundaments. Basic concepts about segmentation.
Structures for controlling functional segmented units.
5. Segmented processors. Basic stages of a segmented processor with a static instructions planning. Types of risks and their possible solutions. Multicicle performance. Dynamic instructions planning. Dynamic jumps prediction.
6. Superscalar structures, supersegmented and VLIW. Superscalar and supersegmented processor concept. Uses of a superscalar processor and of supersegmented ones. VLIW processors.
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